Power Over Ethernet Interoperability By Sanjaya Maniktala

Pages 481
Views 509
Size 15.2 MiB
Downloads 56
Power Over Ethernet Interoperability By Sanjaya Maniktala

Tags:

Contents

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii
Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii
1 The Evolution of Power over Ethernet . 1
Part 1 An Overview of Ethernet
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
A Brief History of Ethernet . . . . . . . . . . . . . . . . . . . . . . 3
Modern Three-Layer Hierarchical Network
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
What Exactly Is “Ethernet”? . . . . . . . . . . . . . . . . . . . . . 12
What Is Interoperability? . . . . . . . . . . . . . . . . . . . . . . . . 18
Part 2 The Historical Evolution of PoE
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Blasts from the Past . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Don’t SWER No More . . . . . . . . . . . . . . . . . . . . . . . . . . 24
The Twisted Pair and the Principle of
Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Common-Mode Rejection by Coils/Transformers
and Other Techniques . . . . . . . . . . . . . . . . . . . . . . . . 29
Immunity and Emissions . . . . . . . . . . . . . . . . . . . . . . . 31
Twist Rate and Wire Diameter . . . . . . . . . . . . . . . . . . . 34
Categories of Ethernet Cable . . . . . . . . . . . . . . . . . . . . 35
PoE Cable Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bandwidth and Information Capacity of Cables . . . . 39
Effect of Temperature on Cable Performance . . . . . . . 41
Cable Temperature Rise Caused by PoE . . . . . . . . . . . 43
The Center-Tapped (Hybrid) Transformer and the
Phantom Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Methods of Injecting PoE via Phantom Power . . . . . 52
PoE Chip Vendors: The Emerging Landscape
of PoE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
2 Overview of PoE Implementations . 57
Power Sourcing Equipment and Powered
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
The Input Voltage Source and Corresponding
Power Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
vi C o n t e n t s PoE on Data or Spare Pairs? . . . . . . . . . . . . . . . . . . . . . 65
Pin Numbering, Colors, and Registered Jacks . . . . . . 68
Telephone Cable to Ethernet Cable . . . . . . . . . . . . . . . 70
Midspan or Endspan? . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Transmission Lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Terminations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Types of Powered Devices . . . . . . . . . . . . . . . . . . . . . . . 82
3 Detection . 85
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Pre-Standard/Legacy Detection Schemes . . . . . . . . . 87
IEEE Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Practical Voltage and Current Limits during
Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Some Practical Detection Techniques . . . . . . . . . . . . . 101
Predetection/Open-Circuit Detection/
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Detection Back Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Detection Signature Resistor Disengagement . . . . . . 107
Lower Detection Threshold: Practical Concerns in
PSEs and PDs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
4 Classification . 111
What Is Classification? . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Types of Classification Methods and Backward
Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Practical Limits of AC-DC Power Supplies . . . . . . . . 115
Classification Is Optional for Type 1 Application
But Recommended . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Default Class (Class 0) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
LLDP or Physical-Layer Classification for
Type 2 PSEs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Class Levels in Layer-1 Classification . . . . . . . . . . . . . 119
1-Event Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Classification “Gray Areas” . . . . . . . . . . . . . . . . . . . . . 126
Reported “Interoperability” Issues . . . . . . . . . . . . . . . 128
Timings during 1-Event Classification . . . . . . . . . . . . 129
Dissipation during Classification . . . . . . . . . . . . . . . . . 129
2-Event Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Timings during 2-Event Classification . . . . . . . . . . . . 131
Overall Timing Constraints . . . . . . . . . . . . . . . . . . . . . . 132
Multiple-Port Compliance and Systems
Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Discharging Port Capacitances and Actual Voltage
“Seen” by the PD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Detection Signature Resistor Disengagement
Concerns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Detection Signature Resistor beyond Detection . . . . 140
IEEE 802.3at Classification Details Summary . . . . . . 142
IEEE 802.3at Table 33-8 Explained Further . . . . . . . . . 145
1-Finger or 2-Finger Classification for
Type 2 PSEs? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
5 Inrush and Power-Up . 149
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Inrush Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Purpose of Inrush Limiting and the PD Bulk
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
Practical PSE Design for Inrush Currents . . . . . . . . . . 154
Undervoltage Lockout Thresholds . . . . . . . . . . . . . . . 158
Analyzing the Inrush Phase . . . . . . . . . . . . . . . . . . . . . 160
Ensuring Proper Power-Up Behavior . . . . . . . . . . . . . 162
Testing the Inrush Performance of PSEs . . . . . . . . . . . 163
A Discrete PD Front-End for Testing PSEs . . . . . . . . . 165
The Inrush Timer and the Real End of Inrush . . . . . . 165
Types of Power-Up Behavior and Power-On . . . . . . . 168
Minimum Inrush Below 30 V . . . . . . . . . . . . . . . . . . . . 169
Type 2 PD Delay Timer . . . . . . . . . . . . . . . . . . . . . . . . . 170
Rise-Time Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Some Practical PD Design Issues . . . . . . . . . . . . . . . . . 173
6 Operation . 177
Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Relevant Sections to Refer To in the AF
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Reasons for Protection . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Brief Overview of Overloads and Shorts as Per
AF Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Testing PSE’s Overload and Short-Circuit Protection
as Per AF Standard . . . . . . . . . . . . . . . . . . . . . . . . . . 182
The Short-Circuit Enigma of the AF (and AT)
Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Device Dependency in the AF Standard . . . . . . . . . . . 184
Evolution of Overload/Short-Circuit Perspective . . . . 185
Short-Circuit Range Comparison (AF and AT) . . . . . 187
General Philosophy in Interpreting the
AT Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Overload and Short-Circuit Requirements as Per
AT Standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Peak Power Calculations . . . . . . . . . . . . . . . . . . . . . . . . 194
and Explained . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Some PSE-Controller Design Suggestions for
AT Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
ICUT Monitoring as Per AT Standard . . . . . . . . . . . . . . . 203
Current Monitoring and Current Limiting
Accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Allowed Port Voltage Sag under Current Limiting . . . . 204
Resumption after “Error” and Timings . . . . . . . . . . . . 206
Summary of Peak and Operating Values . . . . . . . . . . 206
7 Maintain Power and Disconnect . 209
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Keeping the Port Alive . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Dropout versus MPS . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Setting the Timer for “MPS Valid” . . . . . . . . . . . . . . . . 213
PD Preloading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
AC Disconnect and DC Disconnect . . . . . . . . . . . . . . . 213
Commercial PSE’s Interpretation and
Implementation of AC Disconnect . . . . . . . . . . . . . 215
Safety in AC Disconnect . . . . . . . . . . . . . . . . . . . . . . . . 218
Reasons to Avoid AC Disconnect . . . . . . . . . . . . . . . . . 218
8 PoE State-Machine Diagrams . 219
9 Magnetics . 227
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Open-Circuit Inductance (OCL) . . . . . . . . . . . . . . . . . . 228
DC-Bias Current Caused by Baseline Wander . . . . . . 230
Stored Energy and Core Saturation . . . . . . . . . . . . . . . 232
Resistance Imbalance . . . . . . . . . . . . . . . . . . . . . . . . . . . 233
“Imbalance” as Per PoE Standards . . . . . . . . . . . . . . . 234
Current-Imbalance IUNB: What Is It Really? . . . . . . . . . 237
Worst-Case Imbalances and DC Bias . . . . . . . . . . . . . . 238
Derating Power Based on DC-Bias Capability . . . . . . 239
Ballasting Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242
EMI Filtering and Common-Mode Filters
with PoE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Isolation Requirements in Magnetic Components . . . . 247
Hi-Pot Testing for PoE . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Limits on the Y-Capacitance in Magjacks . . . . . . . . . . 252
Vendors Cheating on Y-caps—to Our Advantage . . . . 254
10 Isolation, PCB Design, and Safety . 255
Safety Standards Overview . . . . . . . . . . . . . . . . . . . . . . 255
PoE and Safety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256
Steady and Transient Voltages . . . . . . . . . . . . . . . . . . . 257
Fault Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257
PoE Rails, Ethernet/Telecom Systems . . . . . . . . . . . . . 260
Isolation Requirements . . . . . . . . . . . . . . . . . . . . . . . . . 262
The PoE Hi-Pot Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266
Failing the Hi-Pot Test . . . . . . . . . . . . . . . . . . . . . . . . . . 268
Separation Anxiety . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269
Causes of Isolation Breakdown and Recommended
Minimum Clearance . . . . . . . . . . . . . . . . . . . . . . . . . 269
Summarizing Recommendations for Minimum
Clearance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271
The Concept of Creepage . . . . . . . . . . . . . . . . . . . . . . . 273
Coating versus Noncoating . . . . . . . . . . . . . . . . . . . . . 277
Separations in Inner Layers . . . . . . . . . . . . . . . . . . . . . 278
Minimum Vertical Separation in PCB . . . . . . . . . . . . . 280
Secondary Discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
PD Isolation Requirements . . . . . . . . . . . . . . . . . . . . . . 283
Higher Surge, Cable ESD, and Reliability . . . . . . . . . . 285
Limited Power Source . . . . . . . . . . . . . . . . . . . . . . . . . . 286
11 Surge Testing and Protection . 287
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287
Mandatory versus Custom-Driven
Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Template for Testing during PoE Design
Qualification Phase . . . . . . . . . . . . . . . . . . . . . . . . . . 294
Recommended Surge Test Setup . . . . . . . . . . . . . . . . . 295
What Happens during the Surge Test . . . . . . . . . . . . . 300
Other Setups for Surge Testing . . . . . . . . . . . . . . . . . . . 305
Modeling the Combination Wave Generator
(CWG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306
Recommendations for AC Disconnect . . . . . . . . . . . . 308
Recommendations for Common-Mode Filter
Position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309
Recommendations for DC Disconnect . . . . . . . . . . . . 310
Surviving the 10/700-ms Surge Test . . . . . . . . . . . . . . . 311
Protecting the PD from Surges . . . . . . . . . . . . . . . . . . . 313
Semiconductors for Protection and Some PCB
Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 315
PoE Is an Intrabuilding Standard . . . . . . . . . . . . . . . . . 318
GR-1089 (Telcordia) Requirements . . . . . . . . . . . . . . . 319
ESD Protection of ICs . . . . . . . . . . . . . . . . . . . . . . . . . . . 321
Cable ESD (CDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322
Port Protection Diode in PoE: Any TVS
Required? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324
x C o n t e n t s Should D1 Be a TVS? . . . . . . . . . . . . . . . . . . . . . . . . . . . 328
Appendix: Modeling and Analysis of the
Combination-Wave Generator Used for Surge
Testing (EN 61000-4-5) . . . . . . . . . . . . . . . . . . . . . . . 333
12 Lab Skills, Thermal Management, and
Decoupling . 341
Using Oscilloscopes Wisely (in PoE) . . . . . . . . . . . . . . 341
Measuring PSE Port Voltage . . . . . . . . . . . . . . . . . . . . . 344
Earth Ground Loop Issue and Isolating the
Oscilloscope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345
Thermal Management . . . . . . . . . . . . . . . . . . . . . . . . . . 347
The JEDEC Standards (JESD) . . . . . . . . . . . . . . . . . . . . 350
Types of Test Boards . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352
Improving PCB Thermal Resistance for Exposed
Pad Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Practical Thermal Resistances . . . . . . . . . . . . . . . . . . . . 356
Sizing Copper Traces . . . . . . . . . . . . . . . . . . . . . . . . . . . 357
Calculating Junction Temperature . . . . . . . . . . . . . . . . 357
Different Ways of Specifying Maximum Operating
Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358
Fan Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359
Proper Chip Decoupling . . . . . . . . . . . . . . . . . . . . . . . . 359
13 N-Pair Power Delivery Systems . 361
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361
Starting with Resistance . . . . . . . . . . . . . . . . . . . . . . . . 364
Loop Resistances for N-Pair Power Delivery . . . . . . . 365
Power Estimates for N-Pair Power Delivery . . . . . . . 365
Maximum Power Delivery over Long Distances
Using Available PSEs . . . . . . . . . . . . . . . . . . . . . . . . 367
Impedance Matching for Maximum Power
Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370
The Power Delivery Problem . . . . . . . . . . . . . . . . . . . . 371
Mathematical Solution . . . . . . . . . . . . . . . . . . . . . . . . . . 373
Lowering the PD Undervoltage Lockout . . . . . . . . . . 374
Plotting Power Delivery Curves over Long
Distances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376
Sample Numerical Calculations for N-Power
Delivery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
How Far Will a Given PD Operate? . . . . . . . . . . . . . . . 381
Learning from Telephony . . . . . . . . . . . . . . . . . . . . . . . 382
Four-Pair Implementations . . . . . . . . . . . . . . . . . . . . . . 385
Future Innovation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390
www.Techbooksyard.com
C o n t e n t s xi
14 Auxiliary Power and Flyback Design . 393
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393
Auxiliary Power Option A (Front Aux or FAUX
Pin Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395
Auxiliary Power Option B (Rear Aux or RAUX
Pin Method) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401
Index . 425

Preface

December 2007, San Jose, California: It seems a long time ago.
I walked into a big networking company to head their small
Power over Ethernet (PoE) applications team. Surprisingly,
I hardly knew anything about PoE prior to that day, having been a
switching-power conversion engineer almost all my life. But it
seemed a great opportunity to widen my horizons. As you can see,
one notable outcome of that seemingly illogical career choice five
years ago is the book you hold in your hands today. I hope this small
body of work goes on to prove worthy of your expectations and also
of all the effort that went into it. Because, behind the scenes, there is a
rather interesting story to relate—about its backdrop, intertwined
with a small slice of modern PoE history, punctuated by a rather restive
search for our roots and our true heroes, one that takes us back
almost two centuries.
PoE seemed exciting from the outside, certainly enough for me to
take the plunge. Intuitively, it represented the union of two huge,
hitherto parallel worlds of modern development—power and networking.
It seemed obvious that the scion too would one day mature
into a fine young adult. Soon after taking up the mantle, and the
gauntlet, I somehow managed to resuscitate my skeletal systems
team. Despite that near-heroic effort, even on a good day, we remained
at best a freshly greased jalopy, lurching dangerously from side to
side under the uneven weight of a large heirloom we discovered in
our backseat—one which they insisted was a qualified principal
hardware engineer reporting to me, and I of course begged to differ.
On occasion, I had silently prayed that one day this artifact would
materialize in our PoE lab, and even be spotted moving slowly but
surely toward that dusty ol’ Le Croy oscilloscope! But that was never
meant to be, I was only dreaming. My job was not destined to get any
easier. Finally in 2010, defying all odds (even a sneaky curator along
the way), we somehow managed to get our rickety vehicle, not only
to the finish line, but first—in the entire industry. We had received the
first-ever American safety certification given to a PoE chip, from
Underwriters Laboratories (UL) under their UL 2367 category for
30-watt PoE applications. Yes, it was my tiny team, all pumped up
with steroids, which did that.
What exactly did it bring to us anyway? Bragging rights for sure.
But beyond that, with a UL-certified PoE chip under our belts, we
could enable our customers to drop all their port fuses, a savings of at
least 5 cents on every port on almost all their Ethernet switches and
hubs. That was huge from a commercial viewpoint. Not to be caught
resting on our laurels, barely a few months later, in 2011, we acquired
another industry-first safety certification—the very first PoE chip
certified under the UL 2367 category, but now using four-pair construction,
for enabling 60-W PoE. Keep in mind that, to date, a 60-W
IEEE standard does not exist. This certification was initiated under a
very specific customer request, to support a radical market-driven
standard being pushed by a major original equipment manufacturer
(OEM). That standard, alternatively called UPoE or UPOE, stands for
Universal PoE.1 It seems that just before this OEM reached out to us
in distress, the very launch of UPOE from their side had been put on
indefinite hold on account of UL refusing to certify product safety
based on their existing PoE solution. I was asked to explain, to a
rather sleepless customer late at night, why we stood a far better
chance than the competition of getting them through the UL safety
barrier, and also how much time that would likely take, considering
my previous experiences related to safety testing and of achieving
UL certification. The happy ending was straight out of Bollywood:
the OEM did finally release its new UPOE products, but now completely
based on our PoE chips, the ones we managed to get certified
for up to 60 W barely a few weeks after that telephonic lullaby. It was
delightfully obvious that at least for now, UL certification was no longer
just a case of saving money on fuses—it had turned out that no
one could even legally sell a 60-W PoE solution in the marketplace
without our UL-certified chip, the only one out there at the time. And
so, for a brief moment, our rundown vehicle had dared to pretend it
was a Ferrari.
After this industry-leading UPOE chip certification,2 my company’s
fortunes in this particular business unit turned north, though I doubt
anyone around us really understood the technical reasons for their
unexpected windfall, who delivered it to them, or under what circumstances.
PoE was still considered a niche area (a hobby post, in
effect). To make matters worse, PoE is largely analog electronics at
work, whereas a good part of our modern world is fashionably digital.
In a way, we were therefore low-tech, at least to most people at the
helm. The PoE systems team was, I suspect, not really considered
smart enough to even pass judgment on any one of the hundreds of
“revolutionary” ideas emanating from just one person firmly
ensconced in the hallowed office of the chief technology officer. To
make matters worse, the systems team was now making incredibly
feeble attempts at “incremental ideas” such as the industry’s first
commercially successful single-pair PoE (now appearing in the
emerging automotive PoE market too3—see Fig 13.16). So, finally,
inundated with tons of congratulatory messages that flowed in (not),
shortly thereafter in early 2012 I walked out of what I consider an
inconsequential meeting with someone in urgent need of a backbone,
to join another company down the road, and to continue my PoE
explorations without being forced to make professional compromises.
It seemed a natural career move for me, because this new company
had recently acquired an innovative Israeli company, which
was one of the original pioneers of PoE, as detailed in Chap. 1 of this
book. It would help me “close the loop,” technically speaking. I could
return to the roots of it all and enhance my perspective too. I could
also practice both my power-management and PoE skills under one
roof and under one business unit. And last but not least, it also
allowed me to complete this book relatively unfettered, rather than
having to watch over my shoulder for beady eyes in suits.
In Chap. 1 of this book, I have tried, first and foremost, to give
credit where due, perhaps because I have felt cheated too at times. But
I have also tried to quantify exactly what we, in PoE, owe our past
lives. I am a firm believer that people must declare their inheritance
before showcasing their wealth. We need to recognize and reward the
truly deserving persons, even if they are long gone. Posthumous recognition
does have tremendous value. Many have fought just for a lasting
legacy all their lives, and died for it too. To that end, I have carefully
retraced the history of PoE, and its underlying innovations, deep into
the 19th century. My research points to the startling revelation that PoE
started not at some high-stakes IEEE forum in the 21st century (you
knew that of course), but almost 200 years ago. The real heroes of our
times, largely unsung and unknown today, resided in that era. On
closer examination, a lot of our modern achievements pale in comparison
to theirs, especially when we learn that they had almost no available
resources at their disposal, except sheer resourcefulness and dedication.
Once we become aware of our rich legacy, we realize it is our lack
of historical perspective which often makes us rather self-indulgent
about our own achievements, and often puts us in the embarrassing
position of crowning the wrong heroes of our times—perhaps the first
ones who just happened to walk through the door, or the ones who
spoke the loudest, or perhaps the ones who were just adept at using
modern media or communications to stay in our faces all the time, or
worse, the postman (the marketing or sales guy).
a singular principle of data and power sharing the same lines (or
medium). This principle, often called phantom power today, is much
like two persons sitting on the same seat of a train, oblivious of each
other (with due apologies to J. K. Rowling). I go on to show how the
well-known Wheatstone bridge can be mentally morphed to describe
this fascinating phantom circuit principle, a fact recognized very
early by a man called John Joseph Carty.4 Carty, a former engineer at
Bell Telephone Company, went a step further and replaced the familiar
resistors of the traditional Wheatstone bridge with inductors.
Voilà! In doing so, he had laid the foundations of phantom power
feeding, without which PoE as we know it today would not have
existed. This sequence of events and the birth of the phantom circuit
is recounted in a scanned image of The New York Times dated July 9,
1911, available at The New York Times archives (it has no direct mention
of PoE, though, which is understandable back in 1911).5
All of Carty’s patents can still be found, though as scanned
images only.6,7 We conclude that 1886 is the exact year the phantom
power principle of modern PoE emerged. The National Academy of
Sciences started giving out the John J. Carty Award for the Advancement
of Science, the first recipient being Carty himself, just after 1932,
the year Carty died.8–10
Incidentally, the vaunted twisted-pair cable, which we use freely
today in Ethernet, came from Alexander Graham Bell (hark: the telephone
guy was the cable guy too!)—in 1881.11 It is almost embarrassing
to sense that we may have been patting ourselves on our backs all
along for their achievements, or patting an unknown person with 100
dubiously acquired and questionable patents. Carty and Bell would
surely turn in their graves.
We will notice that through time immemorial, genuine contributors
to society always do it for love, not for money. Money is incidental
in their minds. And that is how some of them brought us to the
point at which modern telecommunications really started to take off.
The ancient patents on which our modern networking world is based
7 http://www.google.com/patents/US348512 and http://www.google.com/patents/
US353350 (though there is a spelling mistake by the Google optical character
recognition software, so his last name is erroneously spelt Caety instead of Carty).
8http://www.nasonline.org/programs/awards/john-j-carty-award.html.
9The fascinating Franklin Institute repository: http://www.fi.edu/learn/case-files/
carty/file.html.
10http://www.fi.edu/learn/case-files/carty/full/clipping.oct2.p1.jpg.
11Look for patent number US000244426 at www.uspto.gov. Or go from here: http://
are probably not too many, their value is not proportional to their
numerical count, but those key patents are indeed rock-solid as it
turns out today. They have not only stood the test of time, they have
changed our times completely—almost 200 years later and still counting.
At the end of the day, any innovation or idea, however it was
acquired or pitched to the general public, must pass a litmus test: can
it hold up to (impartial) technical scrutiny, not just within the organization
or close-knit community it was supposedly created and peerreviewed
in, but by the larger scientific and engineering community?
And not just today, but a hundred years from now? That is the test
which ultimately distinguishes the real Alexander Graham Bells and
J. J. Cartys of yesteryears from some unprincipled modern wannabes.
We remember the sad case of Milli Vanilli in the music world.12 We
also had the sad case of Janet Cooke in journalism.13 More recently,
we had the extremely sad case of Lance Armstrong in sports.14
Extremely sad for us that is, not for them—because we let them do it
to us for that long. There are also perhaps eight impostors in modern
science listed on the Web.15 That is ignominy, not fame. So we ask: are
there any such waiting-to-happen scandals in our brave new networking
world? That could be terribly embarrassing to all, especially
if it turns out that we gave them a stage to strut around on, padded
them with generous financial incentives, and then created an ecosystem
around them based on completely inadequate checks and balances,
one which even protected them ferociously.
I did a fairly comprehensive Web survey while writing this book
and came across a bunch of recently filed PoE patents at the United
States Patent Office Web site.16 I learned that a staggering number of
patents listed there in PoE came from just one person. I counted over
350 U.S. patent applications pending, and another 138 U.S. patents
already granted by the office. A rate of one patent per week or so it
seems, judging by the dates. Is he the new Edison? The new Carty?
The new Bell? How about the father of energy-efficient Ethernet?
Time will tell of course. But I did start to wonder if innovation had
become a numbers game now. Are 100 patents better than one?
Couldn’t that one patent happen to be Alexander Graham Bell’s
famous patent, number 174,465, issued on March 7, 1876—the one
that brought the telephone into our houses?17 I wondered if these 100
modern patents will change the world, or just the lifestyle of their
inventor (and perhaps the inventor’s mentors and carefully chosen
co-inventors too). With these closing thoughts, let us now turn our
12See http://en.wikipedia.org/wiki/Milli_Vanilli.
13See http://en.wikipedia.org/wiki/Janet_Cooke
14See http://en.wikipedia.org/wiki/Lance_Armstrong
15http://healthland.time.com/2012/01/13/great-science-frauds/
16www.uspto.gov
17See http://www2.iath.virginia.edu/albell/bpat.1.html.
www.Techbooksyard.com
xviii P r e f a c e attention to more recent PoE patents, to see how they are perhaps
shaping our world and how they might contribute to the future
growth of technology. Here is a tiny sampling. All are available at
www.uspto.gov or Google Patents at www.google.com/patents. I do
caution: please read the original filings carefully for yourself; judge
for yourself eventually. Assume I am making off-the-cuff and ignorant
remarks. Because the truth is PoE is still evolving, and so are we.
1. U.S. patent number 5,065,133 on November 12, 1991. “Method
and apparatus converting digital signals to analog signals
and simultaneous transmission of AC power and signals
over wire conductors.”18 This patent is perhaps the earliest
modern reference to injecting (AC) power on to the center
taps of data transformers, similar to what we do in PoE today.
2. U.S. patent number 5,994,998, on November 30, 1999. “Power
transfer apparatus for concurrently transmitting data and
power over data wires.”19 This injects DC power on the
center-taps of data transformers, as in modern PoE.
3. U.S. patent number 6,115,468, on September 5, 2000. “Power
feed for Ethernet telephones via Ethernet link.”20 This injects
DC on the center-taps of Ethernet data transformers, as in
PoE today. An extension of the previous ideas.
4. U.S. patent number 8,026,635 B2, on September 27, 2011.
“Power over Ethernet power sourcing equipment architecture
for variable maximum power delivery.”21 This says that if a
PoE chip inside the power sourcing equipment (PSE) has
integrated pass-FETs and thus gets too hot, the PSE chip can
be designed to include a control for driving an external FET
which can be switched in parallel to the main (integrated)
FET. The port current will thus get split, a fraction of it going
through the main (internal) FET, so it will not get too hot—
problem solved. We will learn in Chap. 6 of this book that
there are limits on port current in standards-compliant PoE.
By switching in an external paralleled FET, we actually lose
information about the net port current, because only the
current in the internal FET is being monitored by the PSE.
This idea could work if the PSE can somehow accurately
sense the current in the external FET too, but that aspect is not
addressed.
5. U.S. patent number US 7,956,616, on June 7, 2011. “System and
method for measuring a cable resistance in a power over
18See http://www.google.com/patents/US5065133.
19See http://www.google.com/patents/US5994998.
20See http://www.google.com/patents/US6115468.
21See http://books.google.com/patents/US8026635.
www.Techbooksyard.com
P r e f a c e xix
Ethernet application.”22 This invention uses the available time
between end of classification and power-on to measure the
cable resistance (see Chaps. 4 and 5 of this book). It also
thinks there is an available time slot between detection and
classification, though, after detection, if you raise the port
voltage, any normal PD will assume the PSE is doing
classification. Such minor details aside, as the PSE raises the
port voltage VPORT above about 22 V (see same chapters), a
short-circuit module (SCM) inside the Powered Device (PD)
suddenly conducts and applies a 22-V zener across the port,
causing a certain port current to flow. The inventor bypasses
the problem of infinite currents resulting from short cables
(under an applied voltage source as explicitly stated) and
proceeds to eliminate the zener drop (diode offset) by using
Rcable = (V2 – V1)/(I2 – I1), essentially subtracting two potentially
infinite numbers to produce a finite number always. But we
also need a differential current sensing concept spread across
the time dimension now, so that infinite numbers don’t need to
be processed or stored at all by the chip. It is an inarguably
awesome display of Ohm’s law being used to clobber
conventional number theory.23 We can almost feel the infectious
eagerness with which the inventor’s mentors must have
pursued this idea relentlessly through their brilliant patent
review committee and highly paid law firm. And even I admit,
in such cases, the typical five-figure incentive stock option
award per patent seems rather incongruous. Taking the idea to
the bench, a typical PSE cannot distinguish between a shortcircuit
inside a PD versus a short-circuit on the cable. So it will
jump in to protect from both, by applying current limiting,
eventually turning the port off, as is also evident from Chap. 8
of this book. The PSE will try again and again to power up with
this new-fangled PD placed on the other side. Interoperability
is expected to be the first casualty. This may work with a
proprietary PSE, but it is not backward compatible.
6. U.S. patent number US 8,217,527 B2, on July 10, 2012.
“Midspan powering in a Power over Ethernet system.”24 The
idea of this is that you can inject power into the data pairs by
inserting a center-tapped transformer en route to the PD,
rather than injecting PoE at the starting point (the switch)
itself. Midspan manufacturers may have used this idea for
years.25 Though this inventor omits citing the other patent for
whatever reason, he or she says that this innovation involves
22See http://books.google.com/patents/US7956616.
23http://www.suitcaseofdreams.net/infinity_paradox.htm.
24See http://books.google.com/patents/US8217527.
25See U.S. patent number 7299368 at http://books.google.com/patents/US7299368.
www.Techbooksyard.com
xx P r e f a c e “insertion of inductance at the Midspan to overcome killer
patterns that can cause baseline wander.” Baseline wander is
described in Fig. 9.2 of this book. It is not clear what exact
inductance the inventor is proposing at the Midspan level,
except to suggest it is above 350 μH, same as in any Endspan.
In Chap. 9 of this book we will learn that all practical data
transformers (up to 100 Mbps) have an inductance of over
350 μH, because that happens to be the minimum specified
value. In Fig. 2.9 of this book I have given out another such
method of PoE injection on the data pairs using a Midspan.
Hopefully no one will ask you to pay for that. It is common
sense. This inventor proposes the usual known inductance
value of data transformers, but since it appears that
somewhere in the Ethernet standards it was not explicitly
spelled out that a data transformer could be found inside a
Midspan, or alternatively, someone did not explicitly write
that a Midspan could use a transformer (to inject PoE), the
inventor has claimed rights to it. Though, one option, perhaps,
was to simply bring it to the notice of the IEEE committee to
plug, as most others did. But perhaps this inventor was not
present in those IEEE meetings. That would explain it. So, the
final remaining question is: Is this an innovation which will
change the course of technology?
7. U.S. patent number US 8,082,453 B2, on December 10, 2011.
“Power sharing between Midspan and Endspan for higher
power PoE.”26 Though filed as a separate idea, and much
earlier in time, it actually seems like an extension of the
previous idea, described in number 6 above. Clearly, these
two patents (numbers 6 and 7) have been culled from one.
This part-patent is remarkable. The inventor implies that
instead of just using a simple Midspan to inject power, we
can send power from the switch over the spare pairs to the
Midspan. The Midspan will pass through the power coming
over the spare pairs, but will inject power on to the data pairs
as described in the previous patent (number 6). In effect we
now have power on all four pairs going into the PD, which is
strictly not standards-compliant (is that what the patent
implies?). Note that “N-pair” delivery systems are discussed
in detail in Chap. 13 of this book. One statement in the patent
is noteworthy (see the link in this entry):
For example, one scenario that could occur when no power coordination
between Endspan and Midspan PSE is used includes
both Endspan and Midspan, each independently powering the
26See http://books.google.com/patents/US8082453.
www.Techbooksyard.com
P r e f a c e xxi
PD, thereby providing the PD more than two times its required
power. However, with Endspan having the ability to configure the
first and second output powers, Endspan can have either of the
two PSEs, but not both, power the PD, thereby reducing by a half
the overpowering inefficiency.
In Chap. 3 of this book we will learn that the basic idea behind
back off is simply to never allow the Midspan and Endspan
to power up the cable simultaneously. But here, both the PSEs
(Midspan and Endspan) have somehow powered up. So the
new problem seems to be that the two PSEs are not just
making available, but providing, twice the power needed by
the PD. This is akin to food being forced into someone’s
mouth against his or her wishes, or grain being jammed into
a harvesting thresher, never mind the actual load across the
PD. This spooky overstuffing of the PD results in a catastrophic
situation, which the inventor labels “overpowering
inefficiency.” I am the first to admit the inventor has coined a
novel term here, which may in fact highlight certain process
efficiencies and/or deficiencies of our times, and may lead to
a far more energy-efficient Ethernet.
8. U.S. patent number US 8,217,529 B2, on July 10, 2012. “System
and method for enabling power applications over a single
communication pair.”27 This concerns power delivery over a
single pair. The problem with one-pair PoE is, as explained in
Chap. 13 of this book, that with one pair we no longer have
two available center-tapped nodes for connecting the PoE
forward and return wires. Some PoE engineers have therefore
copied the phantom circuit approach used in audio microphones
and in landline telephones as shown in Fig. 13.16 of
this book. In this particular patent, a separate winding is
placed around the data transformer to counterbalance the
flux produced by the PoE current, thus ensuring we do not
need to oversize the data transformers. However, how do
you derive power to drive this PD flux-cancellation circuitry
(and successfully power up), without having already
powered up? Usually, we cannot afford to bombard magnetic
cores with 350 mA rather than the 8 mA they are probably
designed for. And that is what this patent set out to
accomplish. Did it do that? Does it work? When will it get
built and tested?
Our analysis leads to the conclusion that though there are some great
ideas and some potentially great ideas out there, there is also a great
need for fresh ideas and thinkers to synergize with the remarkable
27See http://books.google.com/patents/US8217529.
www.Techbooksyard.com
xxii P r e f a c e
legacy we inherited. There is still lingering ambiguity in the IEEE
802.3at standard. There is thus a strong need for a book like this one.
I hope you will use it to innovate in a way that makes future generations
look back at us proudly, not askance. Patents are consulted forever.
They form our combined legacy, and are also a fogless mirror of
our times. Therefore, the underlying process behind creation and
innovation is very much worth defending every single day. I do feel
the number-of-patents situation, in particular, stoked by generous
incentive schemes which reward quantity not quality, needs to be
scrutinized. Or we will end up with (more) inventions which aren’t
and inventors who didn’t.
This book does happen to be the very first book on the subject.
I apologize in advance for any unintentional mistakes or misinterpretations.
There are no references other than the IEEE standard to consult
really. The dust has still not fully settled. Please double-check
and validate everything for yourself. I hope this book will help you in
that process and that it will also be fun and enlightening.